The present invention relates to a semiconductor device, and for example, to a technology applicable to a semiconductor device having a transistor using a compound semiconductor layer.
In the field of power semiconductor, the demand for an increase in breakdown voltage and a reduction in resistance is rising. The degree of difficulty in device design of an element using a silicon substrate is increasing because of the adoption or the like of a complicated structure called super junction in order to achieve performance exceeding the physical limit.
In contrast to this, in recent years, development of the field effect transistor using a group III nitride semiconductor has been in progress. Such a transistor includes the HEMT (High Electron Mobility Transistor) using the AlGaN/GaN-based material and the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using the Ga-based material. For example, in the transistor having the AlGaN/GaN heterojunction structure, two-dimensional electron gas is generated at the interface due to polarization by the piezo effect. The two-dimensional electron gas has high electron mobility and a high-carrier density and is capable of giving a low-on resistance and high-speed switching characteristics to the transistor.
In the case where a transistor is used as an element for power control, the transistor is required to have a low resistance and a high breakdown voltage between drain and gate. Furthermore, the transistor using the two-dimensional electron gas is commonly a transistor of normally-on type. In order to reduce power consumption of the transistor, it is preferable to form the transistor into a normally-off type.
In contrast to this, Japanese Patent Laid-Open No. 2009-246292 (Patent Literature 1) describes that it is possible to give both a high mobility and a high breakdown voltage to the GaN-FET by using the electron transit layer using the two-dimensional electron gas as an electric field relaxation layer. Furthermore, Patent Literature 1 describes that the transistor is formed into the normally-off type by separating the electron transit layer by the recess formed so as to reach the electron transit layer. However, in the structure of Patent Literature 1, the threshold voltage and the channel resistance vary considerably depending on the depth of the recess. Furthermore, due to the damage caused by the recess processing, the mobility in the channel part reduces and the channel resistance increases. Because of this, it is difficult to simultaneously achieve a normally-off type, a high mobility, and a high breakdown voltage in the GaN-FET as a whole.
Japanese Patent Laid-Open No. 2011-187623 (Patent Literature 2) describes formation of the electric field relaxation layer by introducing n-type impurities into the p-type GaN substrate without using the two-dimensional electron gas. In detail, Patent Literature 2 describes that the electric field relaxation layer having high mobility and a high breakdown voltage is obtained by setting the sheet carrier concentration of the electric field relaxation layer to 1×1015 cm−3 or more and 5×1017 cm−3 or less.